Static timing analyzers are widely used as tools for optimization and validation of designs of very large scale integrated (VLSI) chips. For example, a VLSI chip design, typically represented by a netlist, may be partitioned into a plurality of successive logic stages of a combinational logic. A logic stage may include, for example, one or more different driver gates such as, for example, a nonlinear driver gate, and one or more interconnect loads. Analysis of a logic stage may be performed or conducted by modeling or simulating nonlinear driver gates inside a logic stage using, for example, simplified linear driver models or current source models. A linear driver model may be generated or created, in some static timing analyzers for example, by following a C-effective procedure as is known in the art.
With the advance of electronic design and aggressive device scaling, electrical characteristics of electronic devices, such as nanometer transistors, are increasingly becoming nonlinear due to increased short channel effects, for example. In addition, ratios of resistance of a typical wire versus a driver also increase proportionally with the scaling. It is becoming increasingly difficult to accurately capture output waveforms of a logic stage at a driver output using a traditional C-effective based linear driver model.
In a netlist, performance of a logic stage may be affected by a neighboring logic stage due to, for example, coupling noises. A logic stage receiving a noise from one or more neighboring logic stages may be a victim stage, referred to herein as a victim or victim stage or victim cell. A logic stage that couples a noise to a neighboring logic stage may be an aggressor stage, referred to herein as an aggressor or aggressor stage or aggressor cell. Switching a driver inside an aggressor stage may cause a noise or a noise glitch being coupled to a victim stage. A noise may usually cause changes in delay of the victim stage which is simultaneously switching. In this case the noise may be known as a delay noise. If a victim stage is quiet, that is the victim stage is not switching, the noise from a switching aggressor stage may potentially propagate through the victim stage, and latch into, for example, a storage element of the victim stage causing a functional failure of the victim stage. A noise causing a functional failure of the victim stage may be known as a functional noise.
Noises or noise glitches that cause functional failure of a victim stage may be modeled, for example, following the C-effective procedure as well. The C-effective procedure based modeling uses two parameters to model the peak and area of a noise, and therefore may be inherently inadequate to capture other characteristics of the noise such as, for example, asymmetric waveforms of the noise. In addition, the C-effective procedure based modeling may not be able to model the driver gates accurately due to increased nonlinearities of the drivers. Furthermore, the C-effective procedure based modeling may require other procedures for performing three-dimensional gate characterization which may include, for example, two glitch parameters and one parameter for output capacitance.
For alignment analysis between an aggressor stage and a victim stage, it was proposed in the art that an approach based on linear driver models may be used. This approach requires the creation of a pre-characterized four-dimensional look-up table and is not based on cell libraries currently existing such as current industry standard cell libraries. Here, the term of alignment refers to a condition, between a victim stage and an aggressor stage, that causes delays or delay noises at the output of the victim stage. A worst-case alignment may be a condition where the victim stage experiences a maximum delay at a driver output. It has been observed that the alignment may be dependent on edge rate, noise width, noise height, and receiver load of the victim cell.
It was also proposed in the art that a nonlinear DC current source model may be used for analyzing timing and noise characteristics of a logic stage. The nonlinear DC current source model may be dependent from input and output voltages. Using this nonlinear DC current source model, a two-dimensional look-up table may be created and augmented with a Miller capacitance (Cm) and an output capacitance (Co) to capture effects of parasitic capacitances. It was shown that using this DC current source model, a fast and relatively accurate analysis may be obtained for arbitrary input waveforms and arbitrary output loads. Some fixed time-step was used for nonlinear simulation of drivers and recursive convolution was used for simulating interconnects. However, this method requires a new library with new characterization data format in order to generate the look-up table. In addition, this method does not address the issue of delay noise analysis.
Another method was presented in the art for calculating changes in delay due to coupling noise at the output of a receiver stage, i.e., victim stage, using nonlinear current source driver models. According to this method, a worst case alignment search may be formulated as a constrained nonlinear optimization problem with an objective to identify relatively large changes, for example, maximum changes, in delay at the output of the receiver stage. This method requires using nonlinear simulation to evaluate noisy responses at the receiver output in order to find an alignment. For a single timing stage, the process of finding an alignment may require several iterations of the nonlinear simulation. As a result, this nonlinear programming (NLP) based method may require significant runtime and may impact the overall efficiency of a static timing analyzer adopting this method. In addition, existing library characterization flow and library formats may also need to be modified in order to obtain a DC current source model explicitly from the SPICE characterization. Such changes are not practically viable since it may require drastic changes in the design and optimization flow.
Responding to the need as described above for modeling nonlinear drivers in a logic stage, the electronic design automation (EDA) industry added new gate characterization data to the standard library format, for example, an effective current source model (ECSM) and a composite current source model (CCSM). Similar to the existing library characterization flow, a gate in ECSM is characterized for a range of input slews and output load capacitances and for each input slew and output load capacitance Cl, a piecewise linear description of the output voltage waveform is provided. ECSM look-up tables are a simple and incremental extension to the traditional delay and output slew look-up tables in a cell library. Similarly, CCSM lookup tables include piecewise linear output current waveforms instead of the output voltage waveforms in ECSM.
It will be appreciated that for simplicity and clarity of illustration, elements shown in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity.